Afzal Malik
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Memory Design Engineer  ·  Bengaluru, India

Afzal
Malik.

VLSI Design Engineer specialising in SRAM, Custom Memory at advanced Technology Nodes & Interested in both Analog and Digital domains of VLSI

01 · About

An Engineer
Working Close
to Silicon.

VLSI Design Engineer with hands-on experience in Memory Design, Simulation & Characterization. My work spans CMOS circuit design, simulation, layout, and system-level integration. I am also interested in analog and digital domain of VLSI.

Strong foundation in CMOS fundamentals, Circuit Analysis, and Verification. Founder of VLSI EDGE — a technical publication for the semiconductor engineering community.

Get in Touch →
CurrentMemory Design Engineer @ STMicroelectronics
Also AtCircuit Design Engineer @ Zia Semiconductor
FounderVLSI EDGE — Technical Publishing Platform
EducationBTech Electronics · AMU · CGPA 9.338
GATE 2025Score 522 · Rank ~2600
LocationBengaluru, Karnataka, India
9.3
CGPA — First Honours (B.Tech)
4+
VLSI Projects
1
IEEE Publication
Merit Scholar
02 · Experience

Where I've Worked.

Oct 2025 – Present · Noida
STMicroelectronics
Memory Design Engineer (Subcon)
Working on memory design projects at advanced nodes with focus on SRAM and custom memory. Circuit analysis, schematic-level design, and industry characterization flows.
Memory Characterization Flow (MCF)ESPCVCUTGENSRAM/ROM CompilerCircuit Design & Simulation
Jul 2025 – Present · Bengaluru
Zia Semiconductor
Design Engineer
Full-time design engineering role focused on semiconductor memory circuit design, simulation, and characterization flows.
Circuit DesignSimulationCharacterizationLayout DesignLinux/Bash/Gvim7nm FinFET/28nm CMOS based Design
Jun 2025 – Present · Remote
VLSI EDGE
Technical Author & Founder
Founded and run VLSI EDGE — a technical publication for the VLSI and semiconductor engineering community. www.vlsiedge.in →
Technical WritingVLSIManagement
Jun 2023 – Jul 2023 · Bengaluru
Mentorship Progarm
Analog Circuit Design Intern
Under Dr. GS Javed (Analog Design Manager @ Intel). Designed and simulated analog building blocks in 180nm CMOS using gm/Id methodology. View Repo →
Analog Circuit DesignOp-Amp180nm CMOSgm/Id methodologyLTSpice
03 · Education
Bachelor of Technology — Electronics Engineering
Aligarh Muslim University  ·  Nov 2021 – Jul 2025  ·  First Class with Honours  ·  CGPA 9.338/10
CMOS Circuits  ·  Analog & Digital VLSI  ·  Semiconductor Devices  ·  Memory Architecture
04 · Projects

Selected Work.

All on GitHub →
01
Phase-Locked Loop Design — 2.4 GHz
Aug 2024 – Jun 2025
PLL Design180nm CMOSLTSpiceNMOS LC VCOTSPC Divider
02
FPGA Neural Network Digit Recognition
Jan 2024 – May 2024
Verilog HDLXilinx VivadoNEXYS A7MNIST
03
Two-Stage Op-Amp Design & Layout — 180nm
Jun 2023 – Jul 2023 · Intel Mentorship
gm/IdLTSpiceADTElectric VLSI
04
CMOS Inverter Design — Schematic to GDSII
Nov 2022
LTSpiceCadence VirtuosoGPDK90GDSII
05 · Skills

Technical Stack.

Proficient across the full VLSI design flow — from schematic entry and simulation through to layout and GDS2 . Experienced in both analog and digital domains.
Technology Nodes
7nm FinFET
28nm CMOS
180nm CMOS
Tools
Cadence Virtuoso | LTSpice | Xschem
Eldo | Primesim XA | NGSpice
Glade | Electric VLSI |
Gvim | Nedit
Xilinx Vivado | FPGA
Linux / Bash / GitHub
Domain Expertise
SRAM & Custom Memory
Memory Design & Characterization
Analog Circuit Design
Schemetic & Layout Design
Languages
Verilog HDL
Python
C
Bash / Shell
06 · Publications

Research.

2024
A 5 GHz Gain-Bandwidth Operational Amplifier in 180nm CMOS Technology
4th IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA 2024) · May 17, 2024 · Bengaluru
Afzal Malik · 5 authors · IEEE CAS Society Bengaluru Chapter
View on IEEE Xplore →
07 · Honours

Recognition.

🏆
Lead Ignite Transform Scholarship (×3)
Aligarh Education Endowment Fund
Thrice recipient for outstanding academic performance during BTech in Electronics Engineering.
🎖
University Merit Financial Award (×3)
Aligarh Muslim University
Three-time recipient for securing a Top 3 position in the Electronics Engineering batch.
📊
GATE EC 2025
IIT Kanpur · Feb 2025
Score 522 · All-India Rank ~2600 in Electronics & Communication Engineering.
🌐
IELTS Academic — Band 7.5
British Council · Oct 2019
Professional working proficiency in English.
Let's work
together.

Open to opportunities in Memory Design, VLSI, and Analog/Mixed-Signal engineering. Reach out for collaborations, roles, or a conversation about semiconductors.

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